The SecretBlaze is a highly configurable and open-source 32-bit RISC soft-core processor, which is based on the instruction set of Xilinx's MicroBlaze. It implements a classic RISC Harvard architecture with a 5-stage pipeline; namely Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA), and Write-Back (WB). Thanks to a pipelined execution, most instructions require one clock cycle to be executed, achieving high-performance at low cost.

The motivation behind this project arises from the need to develop a secure RISC processor for embedded systems.  The main idea is to investigate both hardware and software countermeasures against powerful cryptanalysis techniques called Side-Channel Attacks (SCAs).

Key Features of the SecretBlaze

Architecture - 32-bit / RISC / Harvard

ISA - MicroBlaze

Pipeline - 5-stage

Dhrystone - up to 1.29 DMIPS/MHz (-O2 -fno-inline)

Frequency and Area - 90 MHz / 1460 LUTs on Spartan-3 FPGAs (speedgrade -4) or 240 MHz / 880 LUTs on Virtex-5 FPGAs (speedgrade -3) for the smallest SecretBlaze implementation

Optional Extensions - single-cycle barrel shifter, single-cycle hardware multiplier, hardware divider (2-34 cycles)

Branch Prediction - optional dynamic branch prediction

Cache - optional direct-mapped instruction and data caches

Interrupt - optional interrupt management with an external interrupt controller

Memory Interfaces - Wishbone B4 compatible

Cryptography - optional side-channel resistant implementation